Two-level instruction cache WCET analysis with instruction prefetching
HAN Li-yan
AN Li-kui
Abstract：With the development of hardware in embedded real -time systems, a lot of processors have two-level instruction cache architecture and support instruction prefetching technology .The instruction prefetching can be widely applied in two -level instruction cache only the instruction cache WCET ( Worst-Case Execution Time) with instruction prefetching can be analyzed .Although the cache analysis methods with instruction pre-fetching have already existed , but the researches are limited on the single -level instruction cache and they can-not be applied on the multi -level set-based instruction cache WCET analysis .Through extending the abstract semantics of the instruction cache analysis with the instruction prefetching under the two -level instruction cache architecture , this paper proposes instruction cache WCET analysis method with instruction prefetching based on abstract interpretation .This paper analyzes the effect of instruction prefetching on the cache access latency and abstract cache state for L1 and L2 instruction cache , and then designs the cache access latency computation method and the cache state analysis algorithm with instruction prefetching .The different benchmarks is analyzed in experiment ,and the result shows that our cache WCET analysis method with instruction prefetching is effective ,and instruction prefetching can improve the worst -case performance on an average 19 .3%than that of without instruction prefetching under the different prefetching degrees .
Keywords：Worst-Case Execution Timeabstract interpretationinstruction prefetchingtwo-level in-struction cache
Publication Date：2017-01-01
Online Publishing Date：2025-08-15(First online date of this platform, not the publication date of the document)
Pages：6( 278-283 )