Improved design of virtual FIFO based on FPGA

ZHANG Yu-ping; YE Sheng-jiang

doi:10.7688/j.issn.1000-1646.2016.03.11

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DOI: 10.7688/j.issn.1000-1646.2016.03.11

Improved design of virtual FIFO based on FPGA

ZHANG Yu-ping

YE Sheng-jiang

Keywords：field programmable gate array (FPGA)double data rate 2 (DDR2)first input first output (FIFO)system interconnectionintellectual property corenetwork jittercode streamprogram clock reference (PCR)

Publication Date：2016-01-01

Online Publishing Date：2025-08-15(First online date of this platform, not the publication date of the document)

Pages：6( 298-303 )

Journal of Shenyang University of Technology

PKUISTICEI

ISSN：1000-1646

Year, Vol.(Issue)：2016,38(3)