FPGA-based Design and Implementation of Asynchronous FIFO
Abstract：With the expanding of the density and scale of modern digital circuitry,a system will contain multiple clock.Therefore,the transfer of data between different clock becomes a serious problem needs to be solved.A reliable and feasible solution is asynchronous FIFO.Asynchronous FIFO require very strict clock technology,it is difficult to make the correct design of synthesis and analysis.This paper presents a design method of asynchronous FIFO which based on read/write counter in terms of gray code.This method effectively avoid the metastable state in the data transmission between different clock and given a comprehensive simulation results.
Keywords：multi-asynchronousasynchronous fifoverilog HDLgray code
Publication Date：2012-01-01
Online Publishing Date：2026-08-28(First online date of this platform, not the publication date of the document)
Pages：6( 79-84 )