Design and Implementation of a Securities Market Data Analysis System with Low Latency Jitter
DING Nan
CHAI Zhilei
GAO Haohui
FENG Yifei
ZHANG Xihuang
Abstract：In order to solve the problems of high delay,high jitter,easy blockage,hashing conflict and high maintenance cost in the process of analysis and processing of stock market data by pure software,a cooperative development mode based on OpenCL and HLS is proposed.In Xilinx Alevo U50 FPGA accelerator card,low delay and low jitter are realized by HLS instruction level par-allel flow optimization to improve parallelism,KVS storage optimization to reduce hash conflict,binary search parallel optimization to reduce delay,and dynamic key-value table storage to improve storage utilization.The experiment shows that,compared with CPU I9-9900X 10C20T,the analysis speed is increased by 8 times,the analysis time of single market data is controlled at 189.8ns,and the jitter amplitude is maintained within 14ns.Compared with traditional HDL hardware FPGA development mode,the development efficiency is improved by 3～4 times.It can better adapt to the iterative needs of the financial market.
Keywords：financiallow latency low jittermarket data analysishigh level synthesisfield programmable gate array
Publication Date：2023-11-20
Online Publishing Date：2025-08-15(First online date of this platform, not the publication date of the document)
Pages：7( 2524-2530 )