Serial Test Method of FPGA DDR Module Based on On-Chip Loopback
WANG He
ZHANG Dayu
WANG Yue
ZHANG Song
Abstract：This paper analyzes the feature of DDR module in Virtex FPGA,and designs the test circuit structure of DDR mod?ule based on Loopback method. The structure builds on-chip test circle by FPGA IOBUF modules,and realizes the serial combina?tion test of IDDR and ODDR. Compared with tradition parallel test method,serial test only uses 12 channels of tester and reduces configuration times from 16 to 6. Furthermore,time of DDR module test will decrease remarkably.
Keywords：Key Words FPGADDR moduleon-chip Loopbacktest
Publication Date：2019-01-01
Online Publishing Date：2025-08-15(First online date of this platform, not the publication date of the document)
Pages：5( 24-28 )