An Optimized AES Algorithm and Its FPGA Implementation
ZHANG Wei
GAO Junxiong
WANG Yunbo
WU Wenbin
Abstract：For the encryption and decryption structure of AES is not consistent,an optimized AES algorithm with a unified encryption and decryption process is proposed in this paper.Using the fully pipelined architecture, the proposed circuit achieves an effective tradeoff between speed and resources, among which the S-box and inverse S-box are implemented applying the finite field algorithm based on regular basis.With the analysis of the path delay of each module, the AES round transformation is divided into 6 stages.Results implemented in the Xilinx`s XC7VX485T FPGA show that the hardware resource consumption is 19006LUTs,the maximum frequency is 724.323MHz and the throughput can get to 92.713Gbps, thus obtaining a very good acceleration effect.
Keywords：AESfull pipeliningFPGA
Publication Date：2017-01-01
Online Publishing Date：2025-08-15(First online date of this platform, not the publication date of the document)
Pages：5( 502-505,511 )