Optimization Design of Macro Cell Layout in Physical Design of Integrated Circuits
XIAO Le
LI Jinming
Abstract：With the continuous progress of integrated circuit technology,the integration degree of chips is becoming higher and the process size is becoming smaller and smaller.As a result,the challenges faced by chip physical design are constantly in-creasing.In this context,the reasonable layout planning of macro units in design is particularly important.The traditional macro cell layout planning method has the problems of low efficiency and long time consumption,which not only complicates the design pro-cess but also often fails to meet the requirements of design quality.Although automatic layout planning can improve efficiency,it of-ten faces many challenges in practice,such as an increase in the number of physical rule violations,increased power consumption,and severe congestion.Aiming at the shortcomings of traditional layout and automatic layout methods,a memorywrapper combined with hierarchical physical design method is proposed to control the routing between macro units.Experimental data shows that com-pared to automatic layout and traditional layout,there is a significant improvement in timing results.The establishment time of the worst negative violation(WNS)is reduced by 1.63 ns and 1.41 ns,the total negative violation(TNS)is reduced by about 66％and 52％,the number of violations is significantly reduced,and power consumption is reduced by 17.3％and 10.4％.
Keywords：layout planningdesign constraintshierarchical physical designintegrated circuit
Publication Date：2025-11-20
Online Publishing Date：2026-01-28(First online date of this platform, not the publication date of the document)
Pages：6( 226-231 )