An Iterative and Improved Algorithm for Low Power Data Path Synthesis
PAN Feng
Abstract：In order to solve the problem of high power consumption in data control circuit behavior.This paper discusses the scheduling operation,clock selection,module selection and resource allocation,and proposes an improved algorithm for reducing the power consumption of synthetic data paths.This algorithm uses iterative improvement strategy to avoid minimizing local solutions in search of low power solutions.After considering a variety of module libraries and complex scheduling structures,the supply volt-age and clock selection strategies have been revised to reduce the computational work involved in the calculation of candidate supply voltages and clock cycles.The experiment results show that the algorithm can form a complete data path synthesis system with low power application.
Keywords：data pathpower consumptioniterative algorithmsupply voltageclock cycle
Publication Date：2018-01-01
Online Publishing Date：2025-08-15(First online date of this platform, not the publication date of the document)
Pages：4( 29-32 )