High Speed Parallel Data Transmission System Based on FPGA
ZHAO Yafan
WANG Kun
YANG Fan
BI Tao
Abstract：This system takes FPGA as the core ,while the sender and the receiver of high‐speed parallel data transmis‐sion system have been constituted by two independent FPGA core boards .Transfer protocol adopts 12 bit effective data bandwidth and five cyclic redundancy check code(CRC) ,and transmission rate of bus can reach more than 24 megabits per second .The receiver can be displayed panel data content by LCD after successfully receiving the data which is analyzed by uploading to the PC through the RS232 bus with the transmission rate 9600 BPS .The state of transmission lines is indicated through the LED indicator light on the core board in the process of transmission .The whole system with good modular de‐gree and high integration plays full advantage of flexible and fast practical computing speed .
Keywords：FPGAcheck codeparellel data transmissionRS232
Publication Date：2015-01-01
Online Publishing Date：2025-08-15(First online date of this platform, not the publication date of the document)
Pages：3( 75-77 )