Design of an ultra-high-frequency memristor circuit based on 180 nm CMOS process
YANG Dayi
YU Xinmei
Abstract：This paper presents an ultra-high-frequency integrated memristor circuit designed based on the SMIC 180 nm CMOS process.The circuit utilizes a four-transistor configuration,exploiting the nonlinear switching characteristics of MOSFET and gate voltage control to achieve memristive behavior.The design was simulated and validated using Cadence simulation software.The results indicate that:the proposed memristor circuit features a simple topology with a compact layout area of merely 45 μm2 and a power consumption of 14.04 μW at 1 GHz;operating under a±0.9 V DC supply,the circuit achieves a maximum operating frequency of 1 GHz and exhibits well-defined hysteresis loops across the frequency range from 500 MHz to 1 GHz;the implemented Chua chaotic circuit demonstrates robust chaotic performance,suggesting its potential applications in chaotic integrated circuits,information security,and related domains.
Keywords：integrated memristor circuitultra-high-frequencyhysteresis loop
Publication Date：2025-11-30
Online Publishing Date：2025-12-12(First online date of this platform, not the publication date of the document)
Pages：6( 33-38 )