An all-MOS memristor integrated circuit design for Vilnius chaotic circuits
LI Jiacheng
DUAN Zhikui
Abstract：This paper proposes a low-power memristor integrated circuit based on CMOS technology.Comprising only five transistors,the circuit utilizes parasitic capacitance effects to achieve memristive characteristics,with no need for external biasing.Compared with existing designs,this circuit demonstrates significant advantages in structural complexity,operating frequency,area efficiency,and power consumption,making it suitable for highly integrated neuromorphic hardware systems.The circuit is designed using SMIC 0.18 μm CMOS technology with a 1.8 V power supply,achieving a maximum operating frequency of 100 MHz while consuming only 14.51 μW and occupying a layout area of merely 410 μm2.
Keywords：memristorpinched hysteresisIC
Publication Date：2025-11-30
Online Publishing Date：2025-12-12(First online date of this platform, not the publication date of the document)
Pages：6( 28-32,38 )